A multi-protocol serial interface (MPSI) apparatus is designed to transmit and receive data corresponding to a plurality of protocols between two different devices.
An interface protocol may vary according to whether (i) synchronous or asynchronous operations are performed, (ii) the bit width of bits transmitted at a time, (iii) whether error correction is to be performed, and (iv) whether a strobe signal is applied.
A widely used universal asynchronous receiver/transmitter (UART) consecutively transmits 7 or 8 bits of data. Once a specific voltage level changes from logic high to logic low, the UART senses the change and starts data transmission. By incorporating a stop bit into the last of the consecutive bits, the UART indicates the end of the data transmission.
Pulse-code modulation (PCM) and a serial peripheral interface (SPI) are used to perform data transmission and reception in synchronization with a clock signal and directly transmit and receive binary data.
An audio codec (AC) 97 is used to transmit and receive data in packet form.
A conventional MPSI apparatus is separately designed for each type of protocol. Conventionally, several MPSI apparatuses are included in a single block in order to interface data corresponding to different types of protocols.
FIG. 1A is a block diagram of a general MPSI block 101 including a plurality of MPSI apparatuses.
Referring to FIG. 1A, the MPSI block 101 includes a plurality of MPSI apparatuses 105. In FIG. 1A, four MPSI apparatuses 105 are include in the single MPSI block 101.
FIG. 1B is a block diagram illustrating an example of a structure of the MPSI block 101 illustrated in FIG. 1A.
Referring to FIG. 1B, an MPSI block 131 includes four MPSI apparatuses, and more specifically, UARTs 141 and 142, one Inter-IC Sound (I2S) 143, and one Audio Codec (AC) 97 144. FIG. 1C is a block diagram illustrating another example of a structure of the MPSI block 101 illustrated in FIG. 1A.
Referring to FIG. 1C, an MPSI block 161 includes four MPSI apparatuses, and more specifically, one PCM 171, one UART 172, and first and second I2Ss 173 and 174.
In the MPSI block 131 of FIG. 1B, it is not possible to use three UARTs and to perform an interface using protocols other than those included in the MPSI block 131. In other words, if the MPSI block 131 of FIG. 1B, includes three UARTs it may be difficult to also include PCM, Infrared Data Association (IrDA), or an SPI as an interface in the MPSI block 131 as well.
In the MPSI block 161 of FIG. 1C, it is not possible to use at least two UARTs and to perform an interface using protocols other than those included in the MPSI block 161. Moreover, for an interface using the PCM 171 and the first I2S 173, the UART 172 and the second I2S 174 are not used, degrading the use efficiency of a chip.
As discussed above, a conventional MPSI block or a conventional system-on-chip (SOC) including a plurality of MPSI apparatuses can perform an interface using only a protocol that is initially included during a design stage. As a result, an interface using protocols other than the initially included protocol may be difficult. Moreover, in such a conventional MPSI block or conventional system-on-chip (SOC), several MPSI apparatuses are not used, degrading the use efficiency of the entire MPSI block.